In general, switching transistors of buck-boost DC to DC converter as an integrated circuits that pump out higher output voltage than the input voltage cannot operate properly because the switching transistors fail to do ON and OFF die to the greater output voltage than supply voltage in the integrated circuits.
In case of CMOS transistors, because a gate voltage determines ON or OFF, a PMOS gate turns on the when its voltage is smaller than a source voltage, and the gate turns off when its voltage is larger than a source voltage, the PMOS transistor's gate requires to maintain a voltage that is smaller than its source voltage, or greater than its source voltage.
FIG. 1 is a schematic of a classic DC/DC converter.
In the FIG. 1, a clock generating unit (110) generates clock signals ck1 and ck2; PMOS transistors M1 and M2 turn themselves on when the clock signals ck1 and ck2 are both low, and turn off when the signals ck1 and ck2 are both high.
On the other hand, NMOS transistors M3 and M4 turn themselves on when ck1 and ck2 are both high, and turn off when the both signals are low. Therefore, if the said clock signal ck1 is low, and ck2 is high, then the transistors M1 and M4 turn on, and current ii flows from an input voltage Vi through the transistor M1, an indictor L1, and the transistor M4, charging the indictor in the process.
When the clock signals ck1 is high and ck2 is low, the transistors M2 and M3 turn on, making a circuit consist of the transistors M2 and M3, the indictor L1, and a capacitor C1. The charges within the indictor then go through the transistor M2, ultimately stored in the capacitor C1. By charging up the capacitor C1, an output voltage Vo gradually increases.
Repeated this process and it would continually increase the output voltage Vo if there are no current consuming loads attached.
Yet, source voltage of the DC/DC converter in the FIG. 1 is fixed to Vi, setting the maximum values of clock signals ck1 and ck2 can take. These clock signals go to gates of the transistors M1, M2, M3, and M4 separately. FIG. 2 is a graph of clock signals, input voltage, output current, and output voltage of a classic DC/DC voltage converter.
After a certain amount of time, when an output voltage Vo becomes greater than an input voltage Vi as FIG. 2 shows, the source voltage of the transistor M2 gets greater than maximum value of the clock signal ck2 that goes into the gate of the transistor M2, resulting in the transistor M2's failure in turning itself off even when the signal ck2 is high.
A greater source voltage than the gate voltage within the transistor M2 means that it is unavailable to control the transistor with the clock signals, eventually making it impossible to function as a boost DC/DC voltage converter.
Currently used method to solve such problem stated above is to add within a DC/DC converter a DC voltage amplifier that boosts up Vi, and uses an output voltage of the DC voltage amplifier Vdd as a reference in producing clock signals ck1 and ck2. To ensure proper operations of transistors, these high clock signals ck1 and ck2 are set to have higher value than an expected maximum value of the output voltage Vo. And yet, such a mechanism requires a DC voltage amplifier within a boost DC/Dc converter, plus the clock signals ck1 and ck2 can become unnecessarily huge even when an output voltage is small.